The present disclosure relates to semiconductor devices and methods for manufacturing the semiconductor devices. More particularly, the present disclosure relates to a semiconductor device including a metal-insulator-semiconductor field-effect transistor (MISFET) having a gate electrode including a metal film, and a method for manufacturing the semiconductor device.
In recent years, due to further miniaturization of semiconductor integrated circuit devices, there has been a problem that the short channel effect (SCE) occurs, i.e., as the gate length of the gate electrode decreases, the threshold voltage of the MISFET (hereinafter referred to as a MIS transistor) decreases. To address the problem, a semiconductor device has been proposed which includes a MIS transistor having an offset sidewall (see, for example, Japanese Patent Publication No. 2003-100902).
The benefit of the offset sidewall will be described hereinafter with reference to FIGS. 28A and 28B. FIG. 28A is a cross-sectional view of a configuration of a first comparative example semiconductor device, taken along the gate length direction. FIG. 28B is a cross-sectional view of a configuration of a second comparative example semiconductor device, taken along the gate length direction.
As shown in FIG. 28A, the first comparative example semiconductor device includes a MIS transistor TrA which does not have an offset sidewall. As shown in FIG. 28B, the second comparative example semiconductor device includes a MIS transistor TrB which has an offset sidewall 53b. 
As shown in FIG. 28A, the MIS transistor TrA includes a gate insulating film 51a which is formed on an active region 50x of a semiconductor substrate 50, a gate electrode 52a which is formed on the gate insulating film 51a, and extension regions 54a which are formed in the active region 50x adjacent to the channel region and extending laterally away from the channel region (hereinafter also referred to as “formed in the active region 50x laterally outside the gate electrode 52a”).
As shown in FIG. 28B, the MIS transistor TrB includes a gate insulating film 51b which is formed on an active region 50x of a semiconductor substrate 50, a gate electrode 52b which is formed on the gate insulating film 51b, offset sidewalls 53b which are formed on side surfaces of the gate electrode 52b, and extension regions 54b which are formed in the active region 50x laterally outside the gate electrode 52b. 
The extension regions 54a are formed as follows. An impurity is implanted into the active region 50x using the gate electrode 52a as a mask. As a result, extension implantation regions are formed in a self-alignment manner. Thereafter, the impurity contained in the extension implantation regions is activated by a thermal treatment to form the extension regions 54a. 
The extension regions 54b are formed as follows. An impurity is implanted into the active region 50x using the offset sidewall 53b as a mask. As a result, extension implantation regions are formed in a self-alignment manner. Thereafter, the impurity contained in the extension implantation regions is activated by a thermal treatment to form the extension regions 54b. 
The gate electrode 52a has an effective gate length Leffa represented by:Leffa=La−2×ΔLa where La is the gate length of the gate electrode 52a, and ΔLa is an overlap length across which the extension region 54a and the gate electrode 52a overlap.
The gate electrode 52b has an effective gate length Leffb represented by:Leffb=Lb+2×Wb−2×ΔLb where Lb is the gate length of the gate electrode 52b, Wb is the width of the offset sidewall 53b, and ΔLb is an overlap length across which the extension region 54b, and the offset sidewall 53b and the gate electrode 52b, overlap.
If the gate length La and the gate length Lb are the same (La=Lb) and the overlap length ΔLa and the overlap length ΔLb are the same (ΔLa=ΔLb), the effective gate length Leffb is greater than the effective gate length Leffa by a length (Wb×2) which is two times as great as the width Wb (Leffb>Leffa).
Thus, the effective gate length of the gate electrode can be increased by use of the offset sidewalls.
A relationship between the gate length of the gate electrode and the threshold voltage of the MIS transistor will be described with reference to FIG. 29. FIG. 29 is a diagram showing the relationship between the gate length of the gate electrode and the threshold voltage of the MIS transistor.
As described above, the effective gate length Leffb in the presence of the offset sidewall is greater than the effective gate length Leffa in the absence of the offset sidewall by a length (Wb×2) which is two times as great as the width Wb (Leffb>Leffa).
Therefore, as shown in FIG. 29, the degree of a drop of the threshold voltage in the presence of the offset sidewall (see a thick line) is lower than that in the absence of the offset sidewall (see a thin line). In other words, the effective gate length of the gate electrode can be increased by the presence of the offset sidewall, and therefore, even if the gate length of the gate electrode decreases, the decrease of the threshold voltage of the MIS transistor can be reduced.